1. Field of the Invention
The present invention relates to a data processor having a cache memory, and particularly to a system for reserving coherency of data stored in main memory and data stored in the cache memory.
2. Prior Art
FIG. 1 is a system structure diagram for explaining an operation for maintaining coherency of memory data in a conventional data processor having a cache memory. In this figure, system I comprises a first processor 100 which executes data processing, a main memory 101 and a second processor 102 which executes data processing sharing the main memory 101 with the first processor 100. The processor 100 comprises a cache memory 103 which stores a copy of the contents of the main memory 101 by maintaining the contents with the store-through method for data processing. The first processor 100 and the main memory 101 are connected with a first memory bus 104a, while the second processor 102 and the main memory 101 are connected with a second memory bus 104b. When the processor 102 operates to cause its contents to be stored in the main memory 101, a cache invalidation request signal 105 for requesting invalidation of cache memory 103 is transmitted and completion of the cache invalidating operation by the first processor 100 is notified by a cache invalidation completion signal 106.
FIG. 2 is a logical diagram showing passive invalidation of a store-through cache in a conventional data processor. In this figure, a data processor comprises a cache memory controller 1 which includes a data array in the cache memory 103 and processes a cache memory access from the first processor 100 and a cache memory invalidation request; a tag memory 2 which comprises an address part and a validity indicating part which indicates that memory data corresponding to the address part exists in the cache memory, in order to control, for each cache block, registration of memory data held in the data array within the cache memory controller 1; an invalidation input register 3 which receives a cache invalidation request signal 105 when the second processor 102 requests the main memory 101 to store data; an invalidation address register 4 which receives a cache memory invalidation request address from the first memory bus 104a simultaneously with reception of the cache invalidation request signal 105 by the invalidation input register 3; and an invalidation address comparator 5 which compares the contents of the address part read from the tag memory 2 with the contents of the invalidation address register 4 excluding the address part in the cache block and the address part used for reading the tag memory 2, so as to detect coincidence between those contents. The reference numerals 6, 10, 12 denote AND gates; 9, a NAND gate; 7, 11, OR gates and 8, an invalidation request register for sending an invalidation request to the cache memory controller 1 on the basis of the fact that the cache memory invalidation request address held in the invalidation address register 4 exists in the cache memory 103.
FIG. 3 is a structural diagram of a system for explaining operations for maintaining coherency of memory data in a cache memory of another conventional data processor. In this figure, a system II comprises a first processor 200, a main memory 201, a second processor 102 and a cache memory 103. The first processor 200 and the second processor 102 are connected through a common memory bus 104 for the purpose of getting access to the main memory 201. FIG. 4 is a logical diagram for actively, namely, positively executing invalidation of the store-through type cache memory 103 within the first processor 200 of the system structure shown in FIG. 3. In FIG. 4, the first processor 200 comprises a cache memory controller 1, a tag memory 2, an invalidation input register 3, an invalidation address register 4, an invalidation address comparator 5, AND gates 6, 12, 21, an OR gate 7 and an invalidation request register 8 and is connected as shown in the figure.
Next, an operation for maintaining coherency of memory data in the data processor of the system I will be explained with reference to FIG. 1 and FIG. 2. When the second processor 102 sends a data storing request through the second memory bus 104b to the main memory 101, the main memory 101 updates the contents in accordance with the storing request. If, at the time of the update of data, a copy of the main memory 101 including old memory data to be updated are stored in the cache memory 103 in the first processor 100, it is required to maintain coherency (consistency) of data so that the first processor 100 should not use data not renewed after data has been updated. For this purpose, the main memory 101 sends a cache invalidation request address and a cache invalidation request signal 105 via the first memory bus 104a to the first processor 100 so that a copy of memory data in the cache memory 103 corresponding to the store request issued by the second processor 102 is invalidated. In the first processor 100, the cache invalidation request address is received by the invalidation address register 4 through the first memory bus 104a, while the cache invalidation request signal 105 is received by the invalidation input register 3, respectively. Next, with the output of the invalidation address register 4, the tag memory 2 is accessed to read out the address part and validity indicating part which indicate the situation of registration with regard to a relevant cache block. The address part read from the tag memory 2 is input to the invalidation address comparator 5 and is compared with the content of the invalidation address register 4 excluding the address part to be used to read the tag memory 2 and the address part within the cache block. When the address part coincides with the address part in the invalidation address register as a result of the comparison explained above, the invalidation address comparator 5 outputs a logical 1, and, when these do not coincide, the comparator 5 outputs a logical 0. The validity indicating part indicates whether the data of the cache block corresponding to the invalidation address register 4 and read from the tag memory 2 has been registered validly, and becomes a logical 1 when the data has been registered and a logical 0 when not registered. When three conditions, (1) the invalidation input register 3 outputs a logical 1, namely, the cache invalidation request exists; (2) the output of the invalidation address comparator is a logical 1, namely, the invalidation address coincides with the memory address held by the cache block in the cache memory 103; and (3) a value of the validity indicating part read from the tag memory 2 is a logical 1, namely, the cache memory 103 holds a copy of the main memory 101, are established, the AND gate 6 opens and outputs a logical 1 and thereafter the OR gate 7 opens and outputs a logical 1, thereby putting the invalidation request register 8 in a set condition. On the other hand, when the AND gate 6 opens, the output of NAND gate 9 becomes a logical 0, closing the AND gate 10. Therefore, the OR gate 11 which generates the cache invalidation completion signal 106 does not open. If a copy does not exist in the cache memory 103 when the invalidation input register 3 is in a set condition, namely, when the invalidation address comparator 5 outputs a logical 0 due to no coincidence or when the validity indicating part read from the tag memory 2 is in a logical 0 state which indicates no data has been registered, the AND gate 6 does not open and the signal which places the invalidation request register 8 in a set condition through the OR gate 7 is not generated.
On the other hand, since the NAND gate 9 opens and outputs a logical 1, the AND gate 10 opens and outputs the cache invalidation completion signal 106 through the OR gate 11.
Subsequently, the request for invalidating the data in the cache memory 103 set by the invalidation request register 8 and the cache invalidating address held in the invalidation address register 4 are input to the cache memory controller 1. Upon reception of the request from the invalidation request register 8, the cache memory controller determines priority between access requests to the cache memory 103, accepts the request by the invalidation request register 8 when there is no any other request having higher priority than the cache memory invalidating request, writes the tag memory 2 to put the validity indicating part to a logical 0 state, that is, a non-registered state using the content of the invalidation address register 4, and outputs an invalidation completion message. With the invalidating completion message output from the cache memory controller 1, the OR gate 11 opens and outputs the cache invalidation completion signal 106. Moreover, with the invalidation completion message, the AND gate 12 is closed and outputs a logical 0, thereby clearing the invalidation request register 8.
The main memory 101 which has received the cache invalidation completion signal 106 terminates the processing of writing the store requested data from the processor 102 at a relevant address.
When the second processor 102 reads data from the main memory 101 through the second memory bus 104b, the cache invalidation request signal 105 sent to the first processor 100 is not asserted. Therefore, no cache invalidating operation is initiated in the first processor 100. This operation is common in the following operation and therefore an explanation thereof will be omitted.
Next, with reference to FIG. 3 and FIG. 4 an operation for maintaining coherency of memory data in the data processor of the system II will be explained. The second processor 102 puts a store request on the common memory bus 104 and sends the request to the main memory 201. At the same time, the processor 2 drives a logical 1 indicating to store data by a W/R# signal representing a data transfer direction, that is, whether data is to be stored or fetched, the W/R# signal existing on the common memory bus 104. Next, memory address information in the store request is placed in the common memory bus 104 and the second processor 102 asserts an address strobe signal in order to transfer the memory address information to the main memory 201. When this address strobe signal is asserted, the main memory 201 receives the information in the common memory bus 104 as a store address. At this time, since the W/R# signal is a logical 1, the address strobe signal is asserted in a logical 1 state, and the cache memory controller 1 outputs a logical 0 indicating that the controller is not using the common memory bus 104, the AND gate 21 opens and outputs a logical 1. The logical 1 output from the AND gate 21 is set in the invalidation input register 3 and causes the store address from the second processor 102 on the common memory bus 104 to be sampled and stored in the invalidation address register 4.
Subsequently, the invalidation address comparator 5 and the AND gate 6 decide, by reading the tag memory 2, if a corresponding copy of data of the main memory 201 at the address sampled in the invalidation address register 4 is stored in the cache memory 103, and, when the copy exists in the cache memory 103, the cache memory controller 1 executes an invalidating operation. These operations are the same as those performed in the system I and therefore an explanation of such operations is omitted here.
It is noted that the only a difference between FIG. 4 and FIG. 2 is that cache invalidation completion is not notified to the main memory 201. That is, when the store request of the second processor 102 passes through the common memory bus 104, the first processor 100 can terminate the cache invalidating operation by monitoring traffics of the bus 104, and accordingly the invalidating operation completion need not be notified.
Since conventional data processors are structured such as explained above, if a system structure is different, an operation for maintaining coherency of a cache memory also becomes different. Therefore, different logical structures must be employed, which prevents common use of a processor and forces a new development of processors for each system structure. These changes in system structures have been insufficient. Moreover, in the case where a system structure having a double layered cache is employed, all traffics of a common memory bus must be transferred to a processor bus, resulting in a danger of lowering the performance of a system.